Packet handling based on multiprocessor architecture configuration
US11340932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Jan 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example methods and systems for packet handling based on a multiprocessor architecture configuration are provided. One example method may comprise: in response to receiving a first ingress packet that requires processing by a first virtual central processing unit (VCPU) running on the first node, steering the first ingress packet towards a first receive (RX) queue and performing local memory access on the first node to access the first ingress packet from the first RX queue. The method may also comprise: in response to receiving a second ingress packet that requires processing by a second VCPU running on the second node, steering the second ingress packet towards a second RX queue and performing local memory access on the second node to access the second ingress packet from the second RX queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.