System-on-chip and acceleration method for system memory accessing
US11341062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Jan 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An acceleration technology for accessing system memory, which provides translation agent hardware that calculates the physical address of the system memory based on an access request issued from the device end. The translation agent hardware has a cache memory that stores information to speed up the calculation of the physical address. Each cache line corresponds to a last-recently used (LRU) index value, and the cache line with the greatest LRU index value is preferentially released to be reassigned. A counter counts a count value to show an isochronous caching demand. LRU index values of cache lines assigned to non-isochronous caching are kept not lower than the count value, and thereby isochronous caching takes precedence over non-isochronous caching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.