Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
US11342038B2 · kind B2 · utility
3Cited by
14References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2021 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Jan 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.