System and method for prioritization of bit error correction attempts
US11342044B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Sep 30, 2019 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Apr 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.