Semiconductor device
US11342428B2 · kind B2 · utility
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1References
14Claims
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Key dates
| Filing date | Jan 2, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Jan 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.