RRAM devices with reduced forming voltage
US11342499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2017 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Mar 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.