Method for demodulating digital signals using multiple digital demodulators
US11343127B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 21, 2019 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Jun 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Method for processing a sequence of digital signal samples including a first sub-sequence and a second sub-sequence. Forming a first block of samples comprising the first sub-sequence and a second block of samples comprising header samples followed by the second sub-sequence. Demodulating the first block of samples through a digital demodulator to produce a first block of symbols, and the second block of digital signal samples through a second digital demodulator to produce a second block of symbols. The second demodulator implementing a carrier synchronisation or symbol rate synchronisation starting with the header samples, which comprise samples in a number adapted in such a way that the synchronisation is effective before the second demodulator demodulates the second sub-sequence. Reconstructing a sequence of symbols by concatenating the first symbol block with the second symbol block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.