Interconnect address based QoS regulation
US11343176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2019 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Feb 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.