Hierarchical switching fabric and deadlock avoidance method for ultra high radix network routers
US11343203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Dec 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This invention discloses a hierarchical switching fabric and deadlock avoidance method for ultra high radix network routers. The hierarchical switching fabric comprises a network-on-chip and K multi-port components. The multi-port component comprises a port module configured to receive packets by a high speed serializer/deserializer, code and format the packets, send the packets to a corresponding hyper packet module after coding and format conversion, and send the packets sent by the hyper packet module to the network; and the hyper packet module configured to perform protocol processing for the received data link level packets, discard illegal packets, forward legitimate packets to the network-on-chip, perform data error correcting, format conversion and channel mapping for the packets received from the network-on-chip, and send the packets to the corresponding port module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.