Neural network inference circuit employing dynamic memory sleep
US11347297B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2019 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Nov 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For a neural network inference circuit that executes a neural network including multiple computation nodes at multiple layers for which data is stored in a plurality of memory banks, some embodiments provide a method for dynamically putting memory banks into a sleep mode of operation to conserve power. The method tracks the accesses to individual memory banks and, if a certain number of clock cycles elapse with no access to a particular memory bank, sends a signal to the memory bank indicating that it should operate in a sleep mode. Circuit components involved in dynamic memory sleep, in some embodiments, include a core RAM pipeline, a core RAM sleep controller, a set of core RAM bank select decoders, and a set of core RAM memory bank wrappers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.