Dynamic memory scrambler
US11347899B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 2019 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jul 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory data scrambling system that can dynamically rescramble the contents of a memory while the system is in operation includes an application-specific integrated circuit (ASIC) that has an ASIC bus fabric, a double data rate (DDR) memory controller coupled to the ASIC bus fabric, a dynamic memory scrambler coupled to the DDR memory controller, the dynamic memory scrambler comprising a scrambler, a descrambler, a scrambler selection table, and a key generator and a DDR PHY coupled to the dynamic memory scrambler. The DDR PHY is coupled to an external DDR memory external to the ASIC. The dynamic memory scrambler includes a refresh timer that, upon expiration, causes data in a region of the DDR to be read, descrambled, rescrambled using a different scrambling key, and stored back into the region of the DDR in place of a DDR refresh.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.