Increasing positive clock skew for systolic array critical path
US11347916B1 · kind B1 · utility
5Cited by
3References
20Claims
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Key dates
| Filing date | Jun 28, 2019 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Aug 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock skew may be increased along a critical path of a systolic array. Pipelined registers may be added between a bus that provides input data signals to a systolic array and between a bus that receives output data signals from the systolic array. Skew circuitry for the pipelined registers may be implemented to delay a clock signal to the pipelined registries to allow a clock skew accumulated along a critical path of the systolic array to exceed a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.