Chip layout method based on minimum total wire length
US11347924B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2022 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jan 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chip layout method based on a minimum total wire length, includes: initializing a total wire length to a preset value, initializing a number of iterations, randomly generating a sequence pair to represent a positional relationship between rectangular circuit modules, inputting the sequence pair to a model, and solving to obtain a sequence pair having a minimum wire length within the number of iterations; changing a field operator of the sequence pair to obtain a new one, inputting the new sequence pair to the model, retaining, if an obtained total wire length is less than the original total wire length, the new sequence pair, or otherwise, abandoning the new sequence pair; repeating the above operation till the number of iterations is reached; and outputting a minimum total wire length, and coordinates of each rectangular circuit module to obtain the chip layout based on the minimum total wire length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.