Methods and apparatus for accelerating scan signal fall time to reduce display border width
US11348533B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2020 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Aug 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/045
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The thin-film transistors may be controlled using at least first and second horizontal scan line signals. Loading different data values into any given row in the array may cause the scan line signals to exhibit varying rise/fall times, which results in horizontal crosstalk and luminance non-uniformity across the display. The rise and fall times of the second scan line signal are crucial, so the second scan line signal is driven by two separate scan line drivers formed on both sides of the display. Only the fall time of the first scan line signal is crucial, so the first scan line signal is driven by only one peripheral scan line driver and is coupled to an auxiliary pull-down circuit that is only activated during the pull-down transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.