Patent · US Active

Split replacement metal gate integration

US11348842B2 · kind B2 · utility

0Cited by

8References

15Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Eugenio Dentoni Litta · Leuven, BE
Boon Teik Chan · Wilsele, BE
Steven Demuynck · Aarschot, BE

Key dates

Filing date	Oct 19, 2020
Grant date	May 31, 2022
Priority date	—
Expiry date	Nov 3, 2040

Classification

Technology area (CPC B)Performing Operations; Transporting
CPC primaryB82Y10/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.