Circuits based on magnetoelectric transistor devices
US11349480B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 24, 2019 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Sep 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.