Clock and data recovery and associated signal processing method
US11349485B2 · kind B2 · utility
0Cited by
5References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 16, 2020 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jan 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.