Apparatus and a method for handling non-continuous data transfer for a decision feedback equalizer in a memory subsystem
US11349691B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2021 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jun 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method for handling non-continuous data transfer for a decision feedback equalizer in a memory subsystem. The apparatus includes a plurality of end-of-transfer detection flip-flops configured to sample a read data enable signal; a flag flip-flop; a first logic circuit configured to generate a load enable signal in response to the end-of-transfer detection flip-flops and the flag flip-flop; a second logic circuit configured to generate a load data in response to the end-of-transfer detection flip-flops, the flag flip-flop and the read data enable signal; a plurality of first-in-first-out buffers configured to receive the load enable signal and the load data, and unload the load data as an end-of-transfer indicator in line with data strobe; and a plurality of bypass flip-flops configured to generate a bypass signal in response to the end-of-transfer indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.