High-side gate over-voltage stress testing
US11353494B2 · kind B2 · utility
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4References
15Claims
0Family size
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Key dates
| Filing date | Feb 17, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Mar 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2623
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.