Freeze logic
US11353504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Jun 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/003
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output may be generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.