Clock-error estimation for two-clock electronic device
US11353916B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 17, 2021 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Feb 17, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment method is disclosed for deriving an estimation value of a clock-error for a slave clock, wherein the slave clock is set at a nominal slave period and outputs a sequence of slave clock signals at an actual slave period, and wherein a difference between the actual slave period and the nominal slave period is approximated by the estimation value of the clock-error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.