Centralized access control circuit for controlling access to peripherals
US11354172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Sep 9, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A centralized access control circuit includes a memory, a sub-circuit, and a memory controller. The memory includes a plurality of lock bits mapped to a plurality of bytes of a peripheral register included in a peripheral. The sub-circuit receives, from a processor core, an access request to access a set of bytes of the plurality of bytes. The sub-circuit grants a first level of access privilege to the processor core based on an identifier of the processor core and an address of the set of bytes included in the access request. The memory controller receives the access request and grants, based on a value of each of a set of lock bits mapped to the set of bytes, a second level of access privilege to the processor core. The processor core accesses the set of bytes based on the first and second levels of access privileges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.