Compiler for a command-aware hardware architecture
US11354267B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2021 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Jan 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a compiler for generating command bundles is configured to receive an execution definition that includes operations for execution. The compiler determines an ordered set of hardware functions corresponding to a hardware architecture to execute at least one operation. The hardware architecture may be selected from typical processor types or a command-aware hardware processor. The compiler generates a command bundle that includes a set of logically independent commands based on hardware functions and functionality of the hardware architecture to optimize execution of the operations. A command-aware hardware processor includes a hardware routing mesh that includes sets of routing nodes that form one or more hardware pipelines. Many hardware pipelines may be included in the hardware routing mesh. A command bundle is transmitted through a selected hardware pipeline via a control path, and is modified by the routing nodes based on execution of commands to achieve a desired outcome.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.