Simulation environment for efficient assessment of memory-bound platforms
US11354771B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2021 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Jun 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and computer-readable storage media for providing a simulated graph processing accelerator representative of a hardware-based graph processing accelerator, the simulated graph processing accelerator including a controller component, a set of producer components, and a final merge component; triggering execution of the simulated graph processing accelerator as a simulation of processing of a graph for one or more of breadth-first search (BFS), single source shortest path (SSSP), weakly connected components (WCC), sparse matrix-vector multiplication (SpMV), and PageRank (PR), execution including: generating request streams from each producer component, merging request streams to provide a merged request stream, inputting the merged request stream to a memory simulator, and processing, by the memory simulator, the merged request stream to simulate handling of requests in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.