High bandwidth memory and system having the same
US11355181B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2021 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | May 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.