Semiconductor chip scale package and method

US11355446B2 · kind B2 · utility

Assignee

• Nexperia B.V. · NL

Inventors

• Tobias Sprogies · Hamburg, DE
• Jan Fischer · Lüneburg, DE

Key dates

• Filing date: Dec 16, 2019
• Grant date: Jun 7, 2022
• Expiry date: Mar 23, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2223/54486
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure relates to a semiconductor chip scale package including a semiconductor die. The semiconductor die has a first major surface opposing a second major surface, a plurality of side walls extending between the first major surface and second major surface, a plurality of electrical contacts arranged on the second major surface of the semiconductor die, and an insulating material disposed on the plurality of side walls and on the first major surface. The insulating material includes a machine readable identifier by which a semiconductor chip scale packaging type is identifiable by an identification apparatus that reads the machine readable identifier, and the machine readable identifier includes a colour component.