Patent · US Active

Fully digital glitch detection mechanism with process and temperature compensation

US11355457B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Andreas Lentz · Buchholz, DE
Stefan Heyse · Quickborn, DE
Martin Heinrich Butkus · Hamburg, DE
Oliver Schmidt · Erlangen, DE

Key dates

Filing date	Jun 19, 2019
Grant date	Jun 7, 2022
Priority date	—
Expiry date	Apr 23, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00078
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A fully digital method and apparatus are provided for detecting glitches on a monitored line by providing a toggle signal to an initial delay circuit and a plurality of delay elements formed with standard logic cells so that logic values from the delay elements are captured in a corresponding plurality of clocked capture flops to provide a digitized representation of a delay value during a sampling period which is converted to a numerical measurement result which is evaluated against a reference value to generate an output error signal if a difference between the numerical measurement result and reference value exceeds a programmable margin, where the initial delay circuit is configured with a trim setting to impose an initial delay to compensate for process variations and where the reference value is adapted over a plurality of sampling periods to compensate for temperature effects on the numerical measurement result.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.