Semiconductor device including standard cell
US11355489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Nov 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/981
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.