Memory cell capacitor with varying width and supportive structures
US11355497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Oct 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
A semiconductor device includes a memory cell storing data. The memory cell capacitor includes a plurality of bottom electrodes on a substrate and extending in a vertical direction with respect to a top surface of the substrate, the plurality of bottom electrodes being spaced apart from each other in a first direction parallel to the top surface of the substrate, an upper support pattern on upper lateral surfaces of the plurality of bottom electrodes, and a lower support pattern on lower lateral surfaces of the plurality of bottom electrodes. The lower support pattern is disposed between the substrate and the upper support pattern, and a first bottom electrode of the plurality of bottom electrodes includes a first recess adjacent to a bottom surface of the lower support pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.