Electronic chip memory
US11355503B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2019 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Mar 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes at least three memory cells. For each cell, there is a first doped semiconductor area and a switch coupling the cell to the first area. First doped semiconductor zones connect the first areas together. A memory can include a number of the devices. For example, the cells can be arranged in a matrix, each device defining a row of the matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.