Device integrated with three-dimensional MIM capacitor and method for making the same
US11355579B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Aug 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application relates to the technical field of semiconductor manufacturing, in particular to a device integrated with a three-dimensional MIM capacitor and a method for manufacturing the same. The device comprising: a first dielectric layer, a first conductive metal structure being formed in the first dielectric layer; and a second dielectric layer, plurality of MIM capacitors being formed in the second dielectric layer, the bottom of each of the MIM capacitors being connected to the first conductive metal structure, and the plurality of three-dimensional MIM capacitors being arranged as array in a two-dimensional plane presented by the second dielectric layer; wherein each of the three-dimensional MIM capacitors sequentially comprises an upper electrode, a dielectric layer covering the bottom sides of the upper electrode, and a lower electrode layer covering an outer surface of the dielectric layer; the lower electrode layer is connected to the first conductive metal structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.