Method and circuitry for controlling a depletion-mode transistor
US11356087B2 · kind B2 · utility
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40Claims
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Key dates
| Filing date | Feb 11, 2021 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Feb 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/6875
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.