Transmitter and receiver for low power input/output and memory system including the same
US11356098B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 22, 2021 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Jun 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17788
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.