Hybrid output multiplexer for a high framerate CMOS imager
US11356621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2021 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Mar 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging system is provided that includes a pixel array having a plurality of columns with rows of pixels and with each pixel having a plurality of photodiodes and a common readout circuit that stores respective accumulation voltages from each of the plurality of photodiodes. Moreover, the system includes row driver circuitry that control the pixel array for pixel addressing and readout, such that the respective accumulation voltages of the photodiodes is read out on a readout channel coupled to a bit line column, and a hybrid multiplexer that multiplexes and routes output signals from the pixel array to a video imaging device to be displayed thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.