High speed debug-delay compensation in external tool

US11360143B2 · kind B2 · utility

Assignees

• STMicroelectronics International N.V. · NL
• STMicroelectronics Application GMBH · DE
• STMicroelectronics SA

Inventors

• Avneep Kumar Goyal · Greater Noida, IN
• Deepak Baranwal · Greater Noida, IN
• Thomas Szurmant · Munich, DE
• Nicolas Bernard Grossier · Vimercate, IT

Key dates

• Filing date: Oct 29, 2020
• Grant date: Jun 14, 2022
• Expiry date: Oct 29, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/222
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.