Gate signal control circuit for DDR memory system
US11360709B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.