Dual branch format
US11360774B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Oct 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a branch processing method, comprising: assigning plural branch instructions for a given clock cycle to primary branch information and secondary branch information; routing the primary branch information along a first path having adder logic and the secondary branch information along a second path having no adder logic; and writing the primary branch information including a displacement branch target address to a branch order table (BOT) and the secondary branch information without a target address to the BOT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.