Request buffering scheme
US11360890B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2021 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including a plurality of page circuits and a common request circuit. The page circuits may each be implemented within a respective memory bank controller of a memory bank set and store an address and determine a page hit status. The common request circuit may be implemented within the memory bank set and store client requests and issue a command corresponding to the client requests in response to the page hit status and an order of storage of the client requests. The page circuits may comprise half a storage depth of the common request circuit. The common request circuit may be shared between each of the memory bank controllers of the memory bank set. The memory bank controllers may control access to a random access memory. The address, the client requests and the page hit status may enable buffering to provide a preview of upcoming client requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.