Disjoint array computer
US11360931B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 2021 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | May 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17337
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.