Method and circuit for protecting a DRAM memory device from the row hammer effect
US11361811B2 · kind B2 · utility
2Cited by
2References
31Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 13, 2020 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Nov 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.