Array substrate and method for manufacturing the same and display device
US11362114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2019 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Dec 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
Abstract
A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.