Magneto resistive memory device
US11362266B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Feb 18, 2021 |
| Grant date | Jun 14, 2022 |
| Priority date | — |
| Expiry date | Feb 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N52/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may comprise a substrate defining a main plane; a plurality of memory cells each comprising a SOT current layer disposed in the main plane of the substrate and a magnetic tunnel junction residing on the SOT current layer; and a bit line and a source line to flow a write current in a write path including the SOT current layer of a selected memory cell. The source line comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction of the selected memory cell for assisting the switching of the cell state when the write current is flowing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.