Timer for use in an asymmetric mutli-core system
US11366488B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2021 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | May 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first processing domain configured to run a first operating system and a second processing domain configured to run a second operating system that is different than the first operating system. The integrated circuit further includes a time stamp timer circuit in the first processing domain configured to provide a first time stamp value to the first processing domain and an adjusted second time stamp value to the second processing domain. The time stamp timer circuit includes a timer adjust circuit configured to synchronize the adjusted second time stamp value when a power up signal is received by the time stamp timer circuit from the second processing domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.