Microprocessor with high-efficiency decoding of complex instructions
US11366665B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 2020 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | Sep 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/546
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Microcode combination of complex instructions is shown. A microprocessor includes an instruction queue, an instruction decoder, and a microcode controller. The instruction decoder is coupled to the instruction queue. The microcode controller is coupled to the instruction decoder and has a memory. The memory stores a combined microcode for M complex instructions arranged in a specific order, where M is an integer greater than 1. When the M complex instructions in the specific order have popped out of the first to M-th entries of the instruction queue, the instruction decoder operates the microcode controller to read the memory for the combined microcode with microcode reading trapping happened just once.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.