Completion mechanism for a microprocessor instruction completion table
US11366671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2020 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | Sep 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.