Methods and systems for reducing downtime from system management mode in a computer system
US11366710B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2021 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | Mar 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0787
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for shortening the system management mode when a fault occurs in hardware component in a computer system is disclosed. The computer system has hardware components that may have faults. Notification of an error in one of the hardware components is received through RAS silicon on a processing unit. The error is detected from the hardware component by a system management interrupt handler executed by a bootstrap processor core. The error data is logged into a system error log via a system control interrupt handler executed by the processing unit. The system management mode is avoided during the logging of the error data. This prevents other processor cores being suspended from the system management mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.