Systems and methods for error correction
US11366717B2 · kind B2 · utility
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3References
35Claims
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Key dates
| Filing date | Apr 17, 2018 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | May 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for error correction and a system. The method may include opening a selected row of a memory bank out of multiple memory banks of a dynamic memory module; and while the selected row is open: (i) receiving selected data sub-blocks that are targeted to be written to the selected row, (ii) calculating selected error correction code sub-blocks that are related to the selected data sub-blocks, (iii) caching the selected error correction code sub-blocks in a cache memory that differs from the dynamic memory module and (iv) writing, to the selected row, the selected error correction code sub-blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.