Memory device implementing multiple port read
US11367480B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2020 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | Nov 25, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device provides for a multiple-port read operation, and includes an array of bitcells and a control circuit. Each bitcell of the array includes a write wordline port and a first read wordline port. The control circuit provides an output to the write wordline port, and includes as inputs a write select port and a second read wordline port. In a write mode, the control circuit couples the write select port to the output and disables the second read port. In a read mode, the control circuit couples the second read wordline port to the output and disables the write select port, thereby enabling a multiple-port read operation to the array of bitcells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.