Multi-level memory hierarchy
US11367498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2019 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | Jun 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of hierarchical structuring a multi-level memory in a convolutional neural network, includes partitioning a memory into a plurality of sections, partitioning the plurality of sections into a plurality of stripes, utilizing input data from the plurality of stripes in a MAC array, outputting an intermediate result from the MAC array to at least one of the plurality of stripes of a result buffer, looping back the intermediate result from the at least one of the plurality of stripes of the result buffer to at least one of the plurality of stripes of an input data buffer and outputting a final result from the at least one of the plurality of stripes of the result buffer to at least one of the plurality of stripes of an output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.