Method of fabricating transistor with short gate length by two-step photolithography
US11367615B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | May 1, 2020 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | Aug 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating transistors with short gate length by two-step photolithography is provided. This method utilizes the two-step photolithography by a stepper as well as controlling a first exposed position and a second exposed position to change the gate length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.